The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to forming abrupt source/drain junctions using a diffusion facilitation layer.
In the manufacture of integrated circuit devices it is desirable to reduce the dimensions of the transistors used to form the individual circuits. In the case of field effect transistors (FETs), reducing the channel length provides the capability to deliver a given amount of drive current with a smaller channel width. By reducing the width and length of a FET, the parasitic gate capacitance (which is a function of the area defined by the width and length) can be reduced, thereby improving circuit performance. Similarly, reducing the size of transistors is beneficial in that less area is consumed for a given circuit, and this allows more circuits in a given area, or a smaller, less costly chip, or both.
However, FETs cannot simply be scaled down linearly since, as the width and length attributes of a FET are reduced, other parts of the transistor (e.g., the gate dielectric and the junctions) must also be scaled so as to achieve the desired electrical characteristics. Undesirable electrical characteristics in FETs due to improper scaling include coupling of the electric field into the channel region and increased subthreshold conduction. These effects are sometimes referred to as short channel effects.
A number of methods have been developed to form ever more shallow source/drain junctions for FETs in order to achieve proper scaling. Unfortunately, these very shallow junctions create source/drain extensions that have increased resistivity as compared with deeper source/drain junctions. In longer channel length FETs with deeper source/drain junctions, the source/drain extension resistivity is negligible compared to the on-resistance of the MOSFET itself. However, as MOSFET channel lengths decrease into the deep sub-micron region, the increased source/drain extension resistivity becomes a significant performance limitation.
Source/drain junctions formed by ion implantation have ion distribution patterns or profiles in the substrate that are determined by the ion implantation parameters and the substrate properties. Such ion distributions have a finite (i.e., limited) sharpness or abruptness at their edges. The abruptness is then dulled as the dopant undergoes thermal annealing to make it electrically active in the substrate. Such limited abruptness of the dopant profile, and in particular the limited abruptness of the active portion of the dopant profile, poses limitations on the scalability of such devices to very small sizes.
Various methods have been proposed to sharpen the activated dopant profile at the source and drain junctions. These include solid-phase epitaxial regrowth of a pre-amorphized part of the doped area, as well as shallow and rapid melting of that area by lasers. In both cases, achieved active dopant profiles at the junction can become sharper than the profiles as originally implanted. However, these are complex processes with inherent limitations, and have not fully met the need for better and improved solutions.